The present invention is directed to a system and method for concurrently testing a plurality of semiconductor components such as integrated circuits.
Automated test equipment (ATE) is typically used to test manufactured semiconductor components, such as integrated circuits or the like. The testing system usually includes a tester coupled with a handler. The handler is a placement tool that situates a device under test (DUT), such as an integrated circuit, at a test site within the handler. The tester sends instructions to the handler, such as binning sort information, start/stop signals, and the like for conducting testing of the DUT. The tester is also coupled to the DUT to detect and store results of the testing for reporting to the operator.
Industrial systems connect one tester to one handler. Common handlers can concurrently test integrated circuits using between eight and thirty-two test sites within the handler. However, testers are more often limited to between one and eight test channels. For high pin-count devices, the capability of a tester is often further reduced to two or four channels, or may even be limited to a single channel. Such limitations at the tester result in wasting at least 50-75% of the handler capability.
Handlers are expensive, costing hundreds of thousands of dollars each, and increasing the throughput under the above-described conditions currently requires an increase in the number of handlers. It is therefore desirable to provide a more efficient and cost-effective manner for increasing the throughput of automated circuit testing while using existing testing technology with minimal modification.